\relax \providecommand\hyper@newdestlabel[2]{} \providecommand\HyperFirstAtBeginDocument{\AtBeginDocument} \HyperFirstAtBeginDocument{\ifx\hyper@anchor\@undefined \global\let\oldcontentsline\contentsline \gdef\contentsline#1#2#3#4{\oldcontentsline{#1}{#2}{#3}} \global\let\oldnewlabel\newlabel \gdef\newlabel#1#2{\newlabelxx{#1}#2} \gdef\newlabelxx#1#2#3#4#5#6{\oldnewlabel{#1}{{#2}{#3}}} \AtEndDocument{\ifx\hyper@anchor\@undefined \let\contentsline\oldcontentsline \let\newlabel\oldnewlabel \fi} \fi} \global\let\hyper@last\relax \gdef\HyperFirstAtBeginDocument#1{#1} \providecommand\HyField@AuxAddToFields[1]{} \providecommand\HyField@AuxAddToCoFields[2]{} \newlabel{sec:overview}{{}{1}{Overview}{section*.1}{}} \newlabel{sec:types-of-OS}{{}{1}{Types of Operating System}{section*.2}{}} \newlabel{processes}{{}{2}{Processes}{section*.3}{}} \newlabel{1@xvr}{{}{2}{Processes}{figure.1}{}} \newlabel{1@vr}{{}{2}{Processes}{figure.1}{}} \@writefile{lof}{\contentsline {figure}{\numberline {1}{\ignorespaces The states that a process may be in.}}{3}{figure.1}} \newlabel{fig:states}{{1}{3}{The states that a process may be in}{figure.1}{}} \newlabel{memory-management}{{}{3}{Memory management}{section*.4}{}} \newlabel{2@xvr}{{}{3}{Memory management}{section*.4}{}} \newlabel{2@vr}{{}{3}{Memory management}{section*.4}{}} \@writefile{lof}{\contentsline {figure}{\numberline {2}{\ignorespaces The memory management unit is shown here converting virtual addresses from the \acro {CPU}\xspace to physical addresses.}}{3}{figure.2}} \newlabel{fig:mmu}{{2}{3}{The memory management unit is shown here converting virtual addresses from the \CPU to physical addresses}{figure.2}{}} \@writefile{lof}{\contentsline {figure}{\numberline {3}{\ignorespaces A single-level paging system. Virtual memory addresses are 32-bit. Pages are 4K each.}}{4}{figure.3}} \newlabel{fig:paging}{{3}{4}{A single-level paging system. Virtual memory addresses are 32-bit. Pages are 4K each}{figure.3}{}} \@writefile{lof}{\contentsline {figure}{\numberline {4}{\ignorespaces A multi-level paging system. Virtual memory addresses are 32-bit. Pages are 4K each. The page tables are themselves pages, also of 4K each. Since each page table entry is 4 bytes in size on the Intel platform, there are $1024 = 2^{10}$ entries in each of the page tables. So there are ten bits required for the page number part of the virtual address. The page directory itself is a 4K page, each entry is 4 bytes, so there are 1024 entries, one for each page table. So there are ten bits required for the directory part of the virtual address.}}{4}{figure.4}} \newlabel{fig:multilevel-paging}{{4}{4}{A multi-level paging system. Virtual memory addresses are 32-bit. Pages are 4K each. The page tables are themselves pages, also of 4K each. Since each page table entry is 4 bytes in size on the Intel platform, there are $1024 = 2^{10}$ entries in each of the page tables. So there are ten bits required for the page number part of the virtual address. The page directory itself is a 4K page, each entry is 4 bytes, so there are 1024 entries, one for each page table. So there are ten bits required for the directory part of the virtual address}{figure.4}{}} \newlabel{3@xvr}{{}{4}{Memory management}{figure.4}{}} \newlabel{3@vr}{{}{4}{Memory management}{figure.4}{}}